1. Field of the Invention
The present invention relates to a data processing system, and more specifically to a pipelined data processing system including a synchronous instruction for controlling a stalling and a resumption of a pipelined processing.
2. Description of Related Art
In data processing systems for a signal processing, a system configured to start its processing in synchronism with a periodical event is the most fundamental system. In the signal processing for an audio signal or an image signal, it is an ordinary practice that new data is supplied to the data processing system in synchronism with a sampling rate of the signal, and the data processing system starts a filtering processing or a predicting processing in response to arrival of the data.
In the case that the signal processing is executed in a programmable data processing system such as a CPU (central processing unit) or a DSP (digital signal processor), the number of execution steps changes dependently upon a conditional branch and other factors, and therefore, a periodical event is preferably supplied to the data processing system as an external factor.
In addition, the data processing system is required to have a sufficiently high operation speed for the purpose of complying with a real time signal processing. One means meeting this demand is a pipeline processing in which an instruction execution process is divided into a plurality of stages, for example, an instruction fetch stage (IF), an instruction decode stage (ID), an execution stage (EX1) and a writing stage (WB), so that these stages are simultaneously operated and a stream of instructions are executed in a multiplexed manner.
Furthermore, an interrupt is conventionally used as a means for notifying generation of the periodical event to the data processing system as the external factor. For example, a pulse signal periodically outputted from a timer is supplied to an interrupt request terminal of the data processing system as an interrupt request signal, and a processing to be periodically performed is executed in an interrupt processing routine started by the data processing system when the data processing system has acknowledged the interrupt request.
In addition, if there are a plurality of causes for processings to be periodically performed, it is necessary that the interrupt processing is multiplexed, and therefore, it is necessary to give an order of priority to the plurality of interrupt causes. Accordingly, the system becomes further complicated, and overhead becomes large because of various register savings in a multiple interrupt processing.
Under this circumstance, Japanese Patent Application Laid-open Publication No. JP-A-60-037038 has proposed a means for solving complexity in the multiple interrupt processing, in a microcomputer having a plurality of interrupt causes releasing a halt mode. This will be called a "prior art 1" hereinafter. The microcomputer disclosed in the prior art 1 is configured to select, by means of a program, whether each of the interrupt causes releasing the halt mode releases the halt mode and then performs another interrupt processing, or simply releases the halt mode so as to advance a main program. In response to some timer signals designated by a cause designation instruction, of the plurality of timer signals, it is possible to simply resume the program from a next instruction. Namely, some of the interrupt causes can be processed in a main program.
Furthermore, Japanese Patent Application Laid-open Publication No. JP-A-60-010355 has proposed a method for measuring a utilization rate in a central processing unit by use of a timer counter and an interrupt. In brief, JP-A-60-010355 discloses that a special instruction (halt instruction) is executed in the case of no load so as to start a counting, and when the system is returned to an operating condition, the counting is stopped by an interrupt.
In conclusion, in the pipelined processing system, when a stream of instructions are sequentially executed, a high execution efficiency can be obtained. However, it is a problem that the flow of the pipeline operation is disturbed by for example a conditional branch. In particular, when there occurs an unexpected change of the instruction sequence by for example generation of an external interrupt, the execution of succeeding instructions in the pipeline operation is interrupted, and it is required to newly supply an interrupt processing instruction to the pipelined system. Accordingly, when the external interrupt frequently occurs, the execution efficiency drops remarkably.
Therefore, if the pipelined data processing system performs the signal processing in synchronism with a plurality of timer means (constituting a plurality of interrupt causes) in a multiple interrupt processing mode, the processing efficiency drops.
On the other hand, the prior art 1 discloses a low power consumption microcomputer so adapted that a system clock is stopped in a condition other than an operating condition. Therefore, the stalling and resuming of an instruction is controlled by the stalling and resuming of a timing generator for generating the system clock. However, the stalling and resuming of the system clock results in that a dynamic circuit (in which a stored information will disappear due to the stalling of the system clock) cannot be used. In this connection, it is difficult to identify a range of circuits which allow the stalling and resuming of the system clock.
Furthermore, the prior art 1 is disadvantageous in that it is necessary to minimize a clock skew between the processing system that executes the stalling and resuming of the system clock, and a timer located at an external of the processing system. Because of this reason, it is difficult to apply the processing system based on the prior art 1, to a real-time synchronous processing such as the signal processing.